Number used for 32x1 RAMs   372                  
Number used as Shift registers   70                  
Number of bonded IOBs   23   68   33%            
Number of BUFGMUXs   1   24   4%            
Number of DCMs   1   4   25%            
Number of ICAPs   1   1   100%            
Number of DNA_PORTs   1   1   100%            
Number of ICAP_SPARTAN3As   1   1   100%            
Number of MULT18X18SIOs   7   16   43%            
Number of RAMB16BWEs   16   16   100%            
Average Fanout of Non-Clock Nets   3.77               
 
Performance Summary            [-]      
Final Timing Score:   0 (Setup: 0, Hold: 0, Component Switching Limit: 0)   Pinout Data:   Pinout Report         
Routing Results:   All Signals Completely Routed   Clock Data:   Clock Report         
Timing Constraints:   All Constraints Met            
 
Detailed Reports                  [-]      
Report Name   Status   Generated   Errors   Warnings   Infos         
Synthesis Report                        
Translation Report   Current   Ñð 4. äåê 02:02:24 2019   0   0   2 Infos (0 new)         
Map Report   Current   Ñð 4. äåê 02:02:32 2019   0   21 Warnings (0 new)   5 Infos (0 new)         
Place and Route Report   Current   Ñð 4. äåê 02:03:16 2019   0   0   0         
Power Report                        
Post-PAR Static Timing Report   Current   Ñð 4. äåê 02:03:25 2019   0   0   5 Infos (0 new)         
Bitgen Report                     
 
Secondary Reports         [-]      
Report Name   Status   Generated      

All Implementation Messages Ïò 19. èþí 18:34:52 2020

--------------------------------------------------------------------------------

Program  All Implementation Messages - Errors, Warnings, and Infos New
map WARNING  Pack:266 - The function generator occ/ramx[2].ramx/r6 failed to merge with F5 multiplexer occ/ramx[2].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[2].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[2].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[8].ramx/r6 failed to merge with F5 multiplexer occ/ramx[8].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[8].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[8].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[3].ramx/r6 failed to merge with F5 multiplexer occ/ramx[3].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[3].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[3].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[4].ramx/r6 failed to merge with F5 multiplexer occ/ramx[4].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[4].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[4].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[5].ramx/r6 failed to merge with F5 multiplexer occ/ramx[5].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[5].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[5].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[0].ramx/r6 failed to merge with F5 multiplexer occ/ramx[0].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[0].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[0].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[6].ramx/r6 failed to merge with F5 multiplexer occ/ramx[6].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[6].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[6].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[1].ramx/r6 failed to merge with F5 multiplexer occ/ramx[1].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[1].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[1].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  Pack:266 - The function generator occ/ramx[7].ramx/r6 failed to merge with F5 multiplexer occ/ramx[7].ramx/Mmux__COND_109_3_f5. The function generator occ/ramx[7].ramx/r6 is unable to be placed in the G position because the output signal doesn't match other symbols' use of the G signal. The signal occ/ramx[7].ramx/Mmux__COND_109_5 already uses G. The design will exhibit suboptimal timing.   
map WARNING  PhysDesignRules:372 - Gated clock. Clock net local_j1_read_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.   
map WARNING  PhysDesignRules:372 - Gated clock. Clock net mem_data_rd_reg_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
map WARNING  PhysDesignRules:812 - Dangling pin  on block::.   
ngdbuild INFO  ConstraintSystem:178 - TNM 'CLKA', used in period specification 'TS_clk', was traced into DCM_SP instance DCM_SP. The following new TNM groups and period specifications were generated at the DCM_SP output(s): CLKFX:   
ngdbuild INFO  NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance DCM_SP to 40.000000 ns based on the period specification ( [top.ucf(74)]).   
map INFO  LIT:243 - Logical network j/Mram_dstack10/SPO has no load.   
map INFO  LIT:395 - The above info message is repeated 79 more times for the following (max. 5 shown): j/Mram_dstack11/SPO, j/Mram_dstack12/SPO, j/Mram_dstack13/SPO, j/Mram_dstack14/SPO, j/Mram_dstack15/SPO To see the details of these info messages, please use the -detail switch.   
map INFO  MapLib:562 - No environment variables are currently set.   
map INFO  LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.   
map INFO  PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp vga_ck_gen/DCM_inst/DCM_SP, consult the device Interactive Data Sheet.   
trce INFO  Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).   
trce INFO  Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.   
trce INFO  Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.   
trce INFO  Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.   
trce INFO  Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.   

Mecrisp-Ice 1.2

ok.

words falog f** flog fln (log) fraction integer> >integer lbase epsilon fexp ^fraction
^integer (!) d>u d0< fpow fatan2 facos fasin (fasin) fatan dom2|3 dom3 dom2 (fatan) (taylor2)
2degrees ftan fsincos fcos fsin >range -taylor +taylor (taylor) >taylor rad>deg deg>rad e pi
F# (f#) _f# F.S fd abort" FVARIABLE FCONSTANT >FLOAT -trailing flfrac flexp flint fdigit? flgood
fsign FSQRT d< FE. FS. (E.) R. F. (F.) fsplit F~ F/ F* FMAX FMIN FROUND FLOOR F= F< F- F+ tneg
FROT FNIP FPICK FOVER FSWAP FALIGNED FALIGN FABS F0> F0< F0= F0<> FSIGN? F! F@ FLOATS FLOAT+ S>F
F>D D>F FNEGATE FDROP FDUP FDEPTH FCLEAR SET-PRECISION PRECISION F2/ F2* normalize fshift >exp1
ftemp' expx2 expx1 m1sto m1get fmove 'e2 'e1 'm3 'm2 'm1 longdiv *norm lstemp t+ t2/ t2* sign>exp
exp>sign frshift ud2/ d2/ du< ferror &esign &sign &unsign mxdig bicl ftemp fstak fsp digits -byfp
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u.r .r d.r rtype u. . d. ud. (d.) #> #s # sign hold <# hld BUF BUF0 pick roll spaces */ */mod fm/mod
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cells abs bounds umax umin max min 2over 2swap +! 2dup ?dup 2drop tuck -rot rot true false drop u>
0> 0< > 0<> <> cell+ 0= rdepth @ 1- negate 1+ arshift rshift lshift execute  ok.
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here . 11828  ok.
unused . 3532  ok.
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pi fs. 3.141593e0  ok.
pi f# 1.23456e-775 f/ fs. 2.544706e775  ok.